1. Field of the Invention
The present invention relates to a substrate processing apparatus and a substrate processing method, and more particularly to a substrate processing apparatus and a substrate processing method which are useful for carrying out copper plating on a surface of a ruthenium film, for example, having a thickness of not more than 10 nm, formed in a surface of a substrate, such as a semiconductor wafer, thereby forming LSI interconnects of copper.
2. Description of the Related Art
When copper is used, instead of aluminum, as a material for LSI interconnects, copper plating is generally employed as a method for forming the interconnects.
FIGS. 1A through 1C illustrate, in a sequence of process steps, a process for producing a substrate having such copper interconnects. First, as shown in FIG. 1A, an insulating film 2 of, for example, an oxide film of SiO2 or a film of low-k material, is deposited on a conductive layer 1a, in which semiconductor devices are formed, on a semiconductor base 1, and via holes 3 and trenches 4 as interconnect recesses are formed in the insulating film 2 by the lithography/etching technique. Thereafter, a barrier layer 5 is formed on the entire surface and then a seed layer 7, which serves as a feeding layer in electrolytic plating, is formed on the barrier layer 5. A metal such as tantalum, titanium, tungsten or ruthenium, or a nitride thereof is generally used for the barrier layer 5.
Next, copper plating is carried out onto a surface of the seed layer 7 of the substrate W to fill copper into the via holes 3 and the trenches 4 while depositing a copper film 6 on the insulating film 2, as shown in FIG. 1B. Thereafter, the copper film 6, the seed layer 7 and the barrier layer 5 on the insulating film 2 are removed by chemical mechanical polishing (CMP) so as to make the surface of the copper film 6, filled in the via holes 3 and the trenches 4, substantially flush with the surface of the insulating film 2. Interconnects composed of the copper film 6, as shown in FIG. 1C, are thus formed in the insulating film 2.
In conventional copper plating processes, a copper seed layer, formed by sputtering, CVD, ALD, electroless plating, or the like, has been widely used as the seed layer 7. With the progress toward finer interconnects, such a copper seed layer is becoming increasingly thinner year by year.
In particular, a thickness of a copper seed layer in the field region of a substrate is around 600 angstroms in the manufacturing of the 65-nm generation of semiconductor devices. The thickness of copper seed layer is expected to be not more than 500 angstroms in the 45-nm generation of semiconductor devices, and not more than 300 angstroms in the 32-nm or later generation of semiconductor devices. The side coverage of a copper seed layer, as formed by the most-prevalent sputtering method, is generally 10 to 15%. Therefore, a copper seed layer used in the manufacturing of the 32-nm or later generation of semiconductor devices will have a very small thickness on the order of several tens of angstrom in its portions formed on the side walls of via holes or trenches. The continuity as a seed layer will thus be lost and the function will be insufficient, leading to significantly poorer filling of copper into the recesses. There is therefore a movement to use, instead of sputtering, a more conformal film-forming method, such as CVD or ALD, to form a copper seed layer.
On the other hand, there is an attempt to eliminate a copper seed layer and carry out copper plating directly on a surface of a barrier layer of ruthenium. This is partly because of the instability of a copper material in an atmospheric environment. Thus, copper is easily oxidized in the air, forming a natural oxide film (copper oxide), having a thickness of several angstroms to several tens of angstroms, on a surface of a copper seed layer. Copper oxide is not electrically conductive and is easily soluble in an acidic plating solution.
When copper plating is carried out directly onto a surface of a barrier layer, there is a case, depending on the material of the barrier layer, in which a copper plated film with good morphology as formed by electroless copper plating on a copper seed layer, cannot be obtained or a case in which the plated copper film has poor adhesion to the barrier layer. Further, with the progress toward direct plating on a barrier layer, a thickness of a barrier layer will become several tens of angstroms and the sheet resistance of a barrier layer will become several tens of Ω/□, thus making the terminal effect of a barrier layer more problematic than that of a copper seed layer.
A technique for direct plating onto a barrier layer has been proposed which involves adjusting deposition potentials of barrier layer/copper and copper/copper using a copper sulfate plating solution containing additives, and gradually increasing the electric current applied, thereby filling copper into interconnect recesses covered with a barrier layer (see, for example, US Patent Publication No. 2004/0069648 and U.S. Pat. No. 6,974,531). Though this technique enables uniform filling of copper into interconnect trenches covered with a barrier layer, a thickness of a copper plated film after plating, formed on a substrate, differs between the center and the edge of the film especially when the substrate is a 300-mm wafer, which may cause a problem in a later CMP process.
When there is a passive layer (ruthenium oxide) formed on a surface of a ruthenium film as a barrier layer, copper will be deposited in a particulate form upon direct copper plating of the surface of the ruthenium film (barrier layer), which can cause voids in a fine interconnect pattern and surface roughness of the plated film on the wafer. There is a report that for such a wafer, it is effective to carry out pretreatment (electrolytic processing), prior to copper plating, by using a mixed solution of 1.8 mol/L (17.6 wt %) of sulfuric acid and 1 mmol/L of NaCl as a pretreatment solution (electrolytic solution) and applying a voltage with a ruthenium film as a cathode (see, for example, T. P. Moffat et al., “Electrodeposition of Cu on Ru Barrier Layers for Damascene Processing”, journal of the Electrochemical Society, 153 (1) C37-C50 (2006)). This pretreatment solution (electrolytic solution), because of sodium contained therein, is generally difficult to use in a semiconductor manufacturing process. Further, the 1.8 mol/L (17.6 wt %) sulfuric acid is a dangerous chemical and requires careful handling. The NaCl in this pretreatment solution (electrolytic solution) is considered to act merely as a supporting electrolyte, and the pretreatment solution (electrolysis system) has a considerably high electric conductivity of about 0.6/Ω·cm, as shown in FIG. 6.